FIG. 1 shows a typical single-phase latch design 100 including: a sending latch 101; a receiving latch 103 and combinational logic 105 coupled between sending latch 101 and receiving latch 103.
As shown in FIG. 1, sending latch 101 includes: clock input 115 for receiving a clock signal CLK; first D terminal 107 and data signal D1; second D terminal 109 and data signal D2; first Q terminal 111 and signal Q1; and second Q terminal 113 and signal Q2. Likewise, receiving latch 103 includes: clock input 125 for receiving clock signal CLK; first D terminal 127 and data signal D1′; second D terminal 129 and data signal D2′; first Q terminal 121 and signal Q1′; and second Q terminal 123 and signal Q2′.
Also shown in FIG. 1 are two paths, max path 131 and min path 141, through combinational logic 105. Those of skill in the art will readily recognize that while in FIG. 1 max path 131 and min path 141 are shown as independent, in practice max path 131 and min path 141 are not necessarily independent paths, i.e., max path 131 and min path 141 can converge, diverge or intersect. However, for simplicity of illustration they are shown in FIG. 1, and assumed in the following discussion, to be independent paths.
When latches are used as synchronization elements, for instance when latches are used to separate pipeline stages, there are two important timing constraints that must be taken into account. The first is the potential presence of slow-propagating signals, such as signals through max-path 131 in FIG. 1, which determines the maximum speed at which the system can be clocked. The second is the potential presence of fast propagating signals, such as signals through min-path 141 in FIG. 1 and determines race conditions.
The max-timing problem can be expressed as:
1. Given the maximum propagation delay, i.e., max-path 131, within a pipeline stage, what is the maximum clock frequency the circuit can accommodate? or
2. Given a fixed clock frequency, what is the maximum allowed propagation delay within a stage?
The min-timing problem, also known as “race through” or a “race condition” occurs where the clock signal races ahead of the data stream. The min-time problem typically arises when an early arriving clock sends data through a short, or minimal, logic path, such as min-path 141 in FIG. 1, and this causes the next stage to update before the destination clock samples the previous data. The same result occurs if the destination clock is late. The result is data racing through two or more stages in a single clock cycle. This is a functional, and typically non-recoverable, problem. The min-time problem is particularly problematic because the min-time problem is not related to the clock cycle, i.e., is frequency independent and therefore, in the prior art, could not be fixed by adjusting the clock frequency, as could be done to solve the max-time problem.
FIG. 2 shows the typical single-phase latch design 100 of FIG. 1 and three clock signals: normal clock signal CLK 201 and skewed clock signals CLKe 203 and CLKl 205. As shown in FIG. 2 clock, signal CLKe is early or “skewed” early with respect to clock signal CLK by skew time Tskew 221 and clock signal CLKl is late or “skewed” late with respect to clock signal CLK by skew time Tskew 231.
Clock skew has become an ever-increasing problem as clock frequencies have continued to increase in microprocessor design since the higher the frequency of the clock, the larger percentage of the clock cycle is consumed by a given clock skew. Consequently, clock skew plays an important role with respect to the max-time and min-time problems discussed above.
FIG. 3 shows a signal diagram 300 for a typical synchronous design when operating as designed and when operating under conditions of early clock skew. Shown is the data signal 311 to be sampled including data packets 313, 315 and 317. It is important to note that data stream 311 changes value at points 308, 310, and 312 such that the data value in data packet 313 can be, and often is, different form the data value in data packet 315 or 317, i.e., the data value changes state from data packet 313 to data packet 315 and to data packet 317.
Also shown in FIG. 3 is clock signal CLK 201. As is typical in the present state of the art, signal diagram 300 is for an “edge triggered” system wherein data stream 311 is sampled at the leading edges 324, 326, and 328 of the clock pulses 323, 325 and 327, respectively. Consequently, at time T1301, leading edge 324 of pulse 323 of clock signal CLK 201 causes data to be sampled at point 314 of data packet 313 of data stream 311. Likewise, at time T2303, leading edge 326 of pulse 325 of clock signal CLK 201 causes data to be sampled at point 316 of data packet 315 of data stream 311. Likewise, at time T3305, leading edge 328 of pulse 327 of clock signal CLK 201 causes data to be sampled at point 318 of data packet 315 of data stream 311.
As shown in FIG. 3, when the CLK signal is normal, i.e., clock signal 201, the operation the design is correct and in accordance with design goals since leading edge 324 of pulse 323 samples or reads data packet 313, leading edge 326 of pulse 325 samples or reads data packet 315, and leading edge 328 of pulse 327 samples or reads data packet 317. As long as this is case, and data stream 311 remains synchronous with clock signal CLK 201, the system functions correctly, and the correct data is sampled at the correct time.
However, also shown in FIG. 3 is early skewed clock signal CLKe 203. In this instance the combination of the max-time problem and the early clock skew 350 reduces the maximum clocking frequency in a prior art design. As shown in FIG. 3 skewed clock signal CLKe 203 differs from clock signal CLK 201 in that a leading or “trigger” edge 354 of clock pulse 353 is displaced or “skewed” early, or to the left, with respect to leading edge 324 of clock pulse 323 by skew time 350. Likewise, a leading “trigger” edge 326 of clock pulse 355 is displaced or “skewed” to the left with respect to leading edge 326 of clock pulse 325 by skew time 350. Likewise, a leading “trigger” edge 358 of clock pulse 357 is displaced or “skewed” to the left with respect to leading edge 328 of clock pulse 327 by skew time 350.
The max-time problem arises from the fact that because of skew time 350, leading edge 354 of clock pulse 353 of skewed clock signal CLKe 203 causes data stream 311 to be sampled at time T4307, and point 364 of data packet 302 instead of time T1301, and point 314 of data packet 313. Consequently, data packet 302 is sampled incorrectly instead of the correct data packet 313. Therefore, since the value of data packet 302 can be, and often is, different from the value of data packet 313, incorrect data is sampled and used.
Likewise, because of skew time 350, leading edge 356 of clock pulse 355 of skewed clock signal CLKe 203 causes data stream 311 to be sampled at time T5308, and point 366 of data packet 313 instead of time T2303, and point 316 of data packet 315. Consequently, data packet 313 is sampled incorrectly instead of the correct data packet 315. Therefore, since the value of data packet 313 can be, and often is, different from the value of data packet 315, incorrect data is sampled and used.
Finally, because of skew time 350, leading edge 358 of clock pulse 357 of skewed clock signal CLKe 203 causes data stream 311 to be sampled at time T6309, and point 368 of data packet 315 instead of time T3305, and point 318 of data packet 317. Consequently, data packet 315 is sampled incorrectly instead of the correct data packet 317. Therefore, since the value of data packet 315 can be, and often is, different from the value of data packet 317, incorrect data is sampled and used.
Those of skill in the art will recognize that a similar problem exists for late clock skew such as the clock skew represented by clock signal 205 in FIG. 2. However, in the case represented in FIG. 3, the late clock skew would have to be quite large to affect the data. However, those of skill in the art will recognize that the max-time problem discussed above is not strictly limited to early clock skew, that early clock skew was shown and discussed for illustrative purposes only, and late clock skew could also have been shown for illustrative purposes with similar effect.
In the prior art, one solution for the max-time problem and clock skew problem was to simply slow down the clock signal 203 frequency to the point that uncertainty in the clock arrival did not result in circuit failure. Obviously, slowing down the clock signal frequency had adverse effects on performance and was very undesirable.
Another prior art solution to the max-time problem in latch-based designs was to employ “transparent” latches between stages. In this prior art solution, dual latches were typically employed that were operated “or latched” by complementary clock phases as opposed to a clock leading edge. Consequently, the arrival of the clock was less critical and, when properly employed, a latch-based design could be made fairly insensitive to the max-time problem. However, as discussed below, this prior art solution to the max-time time problem failed to address the other major problem, the min-time problem, and actually made the min-time problem even worse.
One other prior art solution to the max-time problem was the use of pulse latches with a very short transparency period determined by the clock pulse. Unlike flip-flop designs, pulse latch designs required only one latch and were relatively clock skew tolerant for the max-time problem. However, pulse latches are extremely prone to the min-time problem discussed below because, in addition to the clock skew, the transparency period of the pulse latch also needed to be accounted for and designed to when determining potential races.
The max-time problem is well know to those of skill in the art. Consequently, to avoid detracting from the present invention, a more detailed discussion of the max-time problem, and the effects of clock skew on the max-time problem is omitted here. For a more detailed discussion of the max-time problem the reader is referred to virtually any computer engineering text book. For example, “THE COMPUTER ENGINEERING HANDBOOK”, edited by Vojin G. Oklobdzija, CRC press 2002, ISBN 0-8493-0885-1, see chapter 10.2 “LATCHES AND FLIP-FLOPS”, authored by the present inventor, pages 10-35 to 10-52.
As discussed above, the other major clock skew problem, the min-time or “race-through” problem, occurs where the clock signal races ahead of the data stream in a flip-flop based design. The min-time typically arises when an early arriving clock sends data through a short, or minimal, logic path, such as min-path 141 in FIG. 1, and this causes the next stage to update before the destination clock samples the previous data. The same result occurs if the destination clock is late. The result is data racing through two or more stages in a single clock cycle. As also discussed above, the min-time problem is particularly problematic because the min-time problem is not related to the clock cycle, i.e., is frequency independent, and therefore, in the prior art, could not be fixed by adjusting the clock frequency.
The min-time problem is well know to those of skill in the art. Consequently, to avoid detracting from the present invention, a more detailed discussion of the min-time problem, and the effects of clock skew on the min-time problem is omitted here. For a more detailed discussion of the min-time problem the reader is referred to virtually any computer engineering text book. For example, “THE COMPUTER ENGINEERING HANDBOOK”, edited by Vojin G. Oklobdzija, CRC press 2002, ISBN 0-8493-0885-1, see chapter 10.2 “LATCHES AND FLIP-FLOPS”, authored by the present inventor, pages 10-35 to 10-52.
One prior art solution to the min-time problem was to introduce buffer stages in the data stream to slow the data stream to the point that the clock could not race through. Of course, this is a less than ideal solution since it requires additional components and the system must be designed to a worst-case scenario.
In addition, as noted above, in the prior art, one solution for the max-time problem was to simply slow down the clock signal frequency to the point that uncertainty in the clock arrival did not result in circuit failure. However, in the prior art, the min-time problem was frequency independent and therefore could not be solved by such a simple, if inefficient, solution.
In addition, as also noted above, another prior art solution to the max-time problem in latch-based designs was to employ “transparent” latches between stages. In this prior art solution, dual latches were typically employed that were triggered by opposite clock phases. However, the addition of two latches per stage simply aggravated the min-time problem by adding additional opportunities for introduction of race through since race through could happen twice as often, i.e., once per each clock phase.
As also discussed above, one other prior art solution to the max-time problem was the use of pulse latches with a very short transparency period determined by the clock pulse. However, pulse latches are extremely prone to the min-time problem because, in addition to the clock skew, the transparency period of the pulse latch also needed to be accounted for and designed to when determining potential races.
What is needed is a clocking scheme that is clock skew tolerant for both max-time and min-time problems.